In general, the largest representable "unit" of data i na data processor is fixed, thereby inherently limiting the size of operands that can be represented in a single data unit. However, in many data processing applications, it is necessary to perform integer arithmetic, such as addition and subtraction, on data operands which are larger than can be represented in the particular data unit available on the target processor. In order to satisfy this requirement, the arithmetic unit (AU) in the processor must be adapted to support multi-precision integer arithmetic by providing a mechanism for controlling the transfer between instructions of such information as carry-in/borrow-in and carry-out/borrow-out.
In most modern general purpose data processors, the AU supports multi-precision integer arithmetic by allowing arithmetic operations to be "chained". In some of these processors, the instruction set is sufficiently rich to allow the programmer to instruct the AU to provide a carry-out bit if an integer add should result in a carry, or to provide a borrow-out bit if an integer subtract should require a borrow. In such processors, the instruction set usually also allows the programmer to instruct the AU to accept a carry-in bit if a multi-precision integer add is desired, or to accept a borrow-in bit if a multi-precision integer subtract is desired.
In multi-precision processors, the carry control information is typically encoded into the "operation code" (op-code) portion of the integer arithmetic instructions. This technique, however, has two major disadvantages. First, it requires the dedication of a set of op-codes, leaving fewer op-codes for other functions. Second, it requires additional hardware and time to decode this essential control information. It would be advantageous, therefore, to provide a mechanism whereby this carry/borrow control information can be explicitly represented in non-encoded form in the integer instructions.
In addition to multi-precision integer arithmetic, many applications require both signed and unsigned integer arithmetic. In order to satisfy this multi-mode requirement, the arithmetic unit must be adapted, for example, to provide an overflow signal for signed arithmetic if an overflow condition is detected, but to ignore the overflow condition for unsigned arithmetic. In such processors, the instruction set includes allows the programmer to specify either signed or unsigned integer arithmetic. In addition, such processors typically allow the programmer to specify the response of the interrupt hardware to the overflow signal.
In conventional processors having an instruction set which do support multi-precision arithmetic but which lack explicit carry-in/carry-out control, the multi-precision "chain" of instructions is typically immediately preceded by an instruction which prepares the carry bit, typically to zero (0). In addition, in such processors, the chain of instructions must be contiguous since intervening instructions could affect the carry bit. These restrictions could be avoided if the carry control information could be explicitly specified in the instructions.
In multi-mode processors, the carry control information is typically encoded into the op-code portion of the integer arithmetic instructions. This technique, however, has the same disadvantages as in the multi-precision case. It would be advantageous, therefore, to provide a mechanism whereby this signed/unsigned control information can be explicitly represented in non-encoded form in the integer instructions.